Pulse type multiplex communication system



June'z, 1953 C, HANSELL 2,640,921

PULSE TYPE MULTIPLEX COMMUNICTION SYSTEM y @L-ALLA .j E

June 2, 1953 c. w. HANsELl. 2,640,921

PULSE TYPE MLHJTIPLEX COMMUNICATION SYSTEM original Filed .my 17, 194s'1 sham-sheet 2 |770@ deuren .0g/wf darn/7' :v v v v v l INVENTOR.

B" wm June 2, 1953 c. w. HANsELL A 2,640,921

` PULSE TYPE MULTIPLEX COMMUNICATIN SYSTEM v v original mea July 17,194; v sham-sheet s 'n y Tlzl Mom/Agen J/vpar 52) INVENToR.

l 62 fin/65% A51/waz. BYL wie` June 2, 1953 c. w. HANsE| L 2,640,921

, APULSE. TYPE MULTIPLEX COMMUNICATION SYSTEM y Original Filed July 17,1943 7 Sheets-Sheet 4 June 2, 1953 c. w. HANsr-:LL 2,640,921

PULSE TYPE MULTTPLEX COMMUNICATION SYSTEM Original Filed July 17, 1943 7Sheets-Sheet 5 INVENTQR. ,wf/wf WHA/wia. BY l A770/PA/EY June 2, 1953 c.w. HANsELL PULSE TYPE MULTIPLEX COMMUNICATION SYSTEM 7 Shee-ts-Sheet 6Original Filed July 17, 1943 June 2, 1953l c. W. HANsELL yPULSE TYPEMULTIPLE): COMMUNICATION SYSTEM Original Filed July v17', 1945 '7Sheets-Sheet '7 Patented June 2, 1953 PULSE TYPE MULTIPLEX COMMUNICATIONSYSTEM Clarence W. Hansell, Port Jeiierson, N. Y., assignor to RadioCorporation of America, a corporation of Delaware Original applicationJuly 17, 1943, Serial No.

495,181, now Patent No. 2,478,919, dated August 16, 1949. Divided andthis application May 2s, 1949, serial No. 96,124

24 Claims. l

The present invention relates to communication systems employing pulsesoi radio frequency energy which are short Compared to the time intervalsbetween them, and particularly to a multiplex system wherein a pluralityof trains or groups of pulses are transmitted, each group bearing itsown modulation in accordance with the particular message to be conveyedthereby. 'Ihis application is a division of my parent application`Serial No. 495,181 filed July 17, 1943 issued 16 August 1949 as U. S.Patent 2,478,919.

In my copending application, Serial No. 371,- 865, led December 27,1940, now U. S. Patent 2,381,444 granted August 7, 1945 there isdisclosed a pulse type communication system in which the receiver isrendered operative solely at time periods when the signal pulses are dueto arrive. I prefer to call a receiver operated in this manner ashuttered or gated receiver. Advantages of such a system are: (l) Thepeak power at the transmitter can be made to exceed considerably thatwhich is obtainable in a continuous Wave system, by virtue of the factthat the transmitter power is concentrated in the short pulses and (2)that there is obtainable an increase in the signal-to-noise powercompared to continuous wave systems, not only because of the increasedtransmitted power but also because the receiver is responsive onlyduring time periods which may be occupied by the transmitted pulses,thus eliminating the eect of noise and interference occurring betweenpulses.

In accordance with the present invention, there .is provided a multiplexsystem wherein a multiplicity of transmitting channels are operated overa single transmitter to transmit non-overlapping pulses which are veryshort compared to the time intervals between them. The train or group ofpulses from each transmitting station has its own modulation impressedthereon, and the pulses from all transmitting stations occupy only asmall percentage of the total time for all conditions of modulation. Thetransmitter peak power is almost inversely proportional to thepercentage of total time occupied by the pulses, and is thus highcompared to known continuous wave systems. At the receiver, asynchronization system is employed to enable the diierent receivers orutilization circuits to be individually responsive at diierent timesandl solely at those times at which the signal pulses are due to arrive.Thresholding and limiting devices may be employed at the receiver tofurther reduce the noise. Thus, if there are continuous wavetransmitters which might tend to interfere with the pulsing system ofthe invention, the output from the continuous wave transmitters mustreach the receiver of the invention with greaterstrength to produceinterference than with a continuous wave receiver. So long as thereceived strength of the continuous waves is less than the thresholdvalue set at the receiver of the invention, the continuous waves willnot interfere greatly with the operation of the present invention.Likewise, if the continuous Waves do not modulate the signal currentdown to values below the limiting value they will not interfere greatlywith the operation of the .present invention. In general, so long as thepeak amplitude of all noise and interference combined is less than nalithe peak amplitude of the pulse signal, a very great reduction in theeiect of the combined noise and interference may be accomplished by thethresholding and limiting.

In accordance with the present invention, all pulse transmittingstations of the multiplex system will operate from a single transmitterand have the same pulse or repetition rate, although the differenttrains or groups of pulses from the stations will occupy separate timeperiods. A single receiver receives all the pulses, and by means ofsuitable switching or commutating circuits transfers the differenttrains of pulses to the different channels to render them responsivesolely at times when these pulses are due to arrive.

An outstanding advantage for the pulse system of the present inventionemploying a shuttered or gated receiver is that great stability of radiofrequencies in transmitter and receiver is not required. Therefore, thesystem is particularly advantageous for use at the highest radiofrequencies where frequency stability provides a serious problem incontinuous wave systems. The discrimination against noise andinterference made possible by the pulse rate and pulse timingselectivity replaces the selectivity based upon close control of radiocarrier frequencies, which is relied upon in continuous wave systems.

A more detailed description of the invention will now be given, inconjunction with a drawing, wherein:

Fig. l schematically illustrates the transmitting end of a pulse typemultiplex communication system, in accordance with the presentinvention;

Figs. 2 to 6 schematically illustrate details of p different pulsedelayer circuits which can be used in the transmitting system of Fig. 1;

Figs. '7 and 8 schematically illustrate details of diiTerent types ofpulse modulation circuits which can be used in the transmitting systemof Fig. 1;

Fig. 9 schematically illustrates `the receiving end of a pulse typemultiplex communication system in accordance with the present invention;

Fig. 10 schematically illustrates the details of a pulse controlledswitcher circuit which can be used in the receiving system of Fig. 8;and

Figs. 11 and 12 show different embodiments of individual receivers forreceiving and demodulating pulses sent out from a remote transmitter.

Referring to Fig. 1, there is shown in block diagram a pulse typemultiplex transmitter" suitable for the transmission of pulses which aremodulated in length or timing. This transmitter includes a pulse keyedradio frequency amplifier l which is supplied with radio frequencyexcitation from a constant radio frequency oscillator II. Transmitter I0is provided with vacuum tube keying equipment capable of causing thetransmission of very short pulses in response to short input pulses. Theoutput from the transmitter I0 passes over a suitable transmission lineI2 to an antenna system I3, here shown, by way of example only, as adirective antenna in the form of a parabolic reflector having a dipoleat its focus. A pulse oscillator I4 produces pulses at a constant rate,which pulses are short compared with the time spacing between them.

These pulses are repeated at a frequency above the highest modulationfrequency, and are delivered to pulse modulators I5, I6, ll, etc. and toa pulse delayer 20. The pulse modulators I5, I6 and have respectivelyimpressed thereon modulation inputs from leads I', I6' and I'|, in orderthat the outputs of these modulators consist of trains or groups ofpulses suitably modulated in accordance with the intelligence to beconveyed on the dierent channels. The outputs from the pulse modulatorsI5, I6, Il, etc. are respectively delivered to pulse delayers and keyers2|, 22, 23, etc. These pulse delayers are adjusted for diierent delaysin order to provide pulses which constitute the input to the transmitteror pulse keyed radio frequencyampler I0. The pulses delivered to thetransmitter I0 from the delayer circuits are preferably equally spacedin time, on the average, and recur at a pulsing'rate equal to the rateof the pulse oscillatorl I4 multiplied by the number of pulse delayermodulators. Obviously, the pulse outputs from the diiferent channels(each of which includes a pulse modulator and delayer circuit) areindependently modulated for the transmission of independent programs ormodulations.

The pulse delayer circuits 20, 2|, 22', 23, etc. pass pulses at thesamerepetition rate as the pulse oscillator I4 but at different times.Thus, if the pulse modulator circuits modulate the length of the pulses,for example, the, transmitter will send out constant frequency butVariable length pulses separated in time. If, however, the pulsemodulators modulate the vtiming of the pulses, the transmitter I0 willsend out timing modulated pulses Whose average frequency is the same butwhich are retarded or advanced in time by the modulation. l p

The pulses from each delayer circuit are short compared to the timeintervals between them, in order that the pulses from all the `channelsoccupy only a small percentage of the total time for all conditions ofmodulation. Thus, as an example, a 5 channel telephone multiplex systemincluding a synchronizing channel might have a pulse rate in eachchannel of 10,000 per second, in which case the average spacing betweencenters of continuedfpulses' will bev 20'micro-seconds. The pulse lengthmay be on the order of a half micro-second. For this example, it will beevident that the percentage of time occupied by all pulses'in each cycleof operations for all conditions of modulation may be only 2.5% of thetotal elapsed time, as measured from the beginning of one` pulseItransmitted by the first channel to the'b'eginning of the next pulsetransmitted 'from the same channel in one complete cycle of operations.'With this percentage of operating time the transmitter I0 can provideon the order of 40 times as much peak power as can be obtained from'a;continuous wave transmitter of equal size and cost.

It should be noted that the pulse oscillator I4 impresses its outputdirectly upon the pulse delayer and keyer 20 without the intermediary ofa pulse modulator circuit. This arrangement is preferred because it isdesired that the pulses from the output of the pulse delayer 20 be therst ones received at the receiver, andthese pulses employed tosynchronize or render operative the various receiving circuits solely atthose time periods when the signal'pulses for the respective channelsare due to arrive. In View of the slight delay' occasioned in the systemof the invention in rendering the receiving circuits sequentiallyoperative after the receipt of the rst pulse, it is preferred that therebe no modulation impressed on the synchronizing pulses, in accordancewith the preferred embodiment of the present invention. This featurewill be described in more detail later in connection with the receivingsystem of Fig. 9. y

Figs 2, 3, 4, 5 and 6 show diiferent types of pulse delaying circuitswhich can be employed in the system of Fig. 1.

vReferringto Fig. 2 in more detail, there is shown a triode vacuum tube30 to whose grid is supplied an input pulse through a transformer 3|.A'positive polarizing potential is supplied to the anode of the vacuumtube through a variable resistor 32 and the primary winding of atransformer 33. A condenser 34 is connected between the cathode of thetriode and the junction between the resistor 32 and the primary windingof the" transformer 33. In circuit with the cathode as shown, there isprovided av condenser 35 which is shunted by a resistor 36 the timeconstant'of which circuit is a measure of the desired Adelay between theinput pulse and the output pulse. The time delayed output pulse is takenfrom the secondary winding of the transformer 33. Vacuum tube 30is` sobiased that it is normally conductive (that is, passes anode current inthe absence of an input pulse). In this condition, a current will flowfrom the positive polarizing'source through the resistor 32 and throughthe primary winding of transformer 33, thus shunting or Icy-passingcondenser 34. An incoming pulse applied to the transformer 3| will drivethe grid of the triode momentarily positive to charge the condenser 35,due to grid rectification,` as a result of which a negative charge'isplaced on the grid of the tube 30, thus biasing the tube,A and renderingit non-conductive. When the4 tube 30 becomes non-conducting, currentwill iiow from the positive anode polarizing s ourcethrough thecondenser 34 to ground, andwill'thuscharge vthe condenser34. When thechargeon kcondenser''35 leaks off through its shunt connected resistor36, the grid will approach a state of zero potential relative to thecathode, at which time the tube will pass current, thus enabling thecondenser 34 to discharge across the tube. A pulse is thus passedthrough the transformer 33 .whose time of occurrence is controlled bythe adjustment of the grid resistance 36, the latter determining thelength of time it takes for the charge on condenser to leak off. Therate of repetition of the pulses across the transformer 33 is, ofcourse, determined by the repetition rate of the .input pulses. Theperiod of discharge of the condenser 35 should be less than the timespacing between the incoming pulses, to which the output pulses areresponsive, and should correspond to the relative time delay desired inpulse delayer and keyer units 20, 2|, 22 and 23 of Fig. 1.

Fig. 3 shows an arrangement which is similar to Fig. 2, except that thevacuum tube 30 is a screen grid tube and the condenser 34' is in thescreen grid circuit. The elements which are common to Figs. 2 and 3 havebeen given the same reference numerals, and this applies to Fig. 4 also.Since condenser 34', resistor 32' and vacuum tube 30' of Fig. 3respectively serve the same purpose as condenser 34, resistor 32 andvacuum tube 30 of Fig. 2, they have been given the same referencenumerals except for the prime designations. Tube 30 is normallyconductive and except for the structural differences hereinabove noted,the operation of Fig. 3 is substantially the same as the operation ofFig. 2.

Fig. 4 is an arrangement similar to Fig. 3 with the exception that thereare employed in Fig. 4 two condensers 34 and 34' which charge anddischarge simultaneously, thus providing a sharper output pulse from thetransformer 33. It should be noted that condensers 34 and 34' areconnected to the positive polarizing potential through separateresistors 32 and 32', respectively. Except for the structural dierencesnoted, the operation of Fig. 4 is substantially the same as that ofFigs. 2 and 3.

The pulse delay circuit of Fig. 5 includes a triode electrode structure4|) and a diode electrode structure 4| which, although shown in separateenvelopes, may, if desired, be included within a single envelope. Thetriode 4|) is normally conductive (that is, passes current in theabsence of an input pulse applied to transformer 3|). During theconductive condition of tube 40, the condenser 43 which is connectedacross the cathode and anode through a winding of output transformer 42,is shunted out or by-passed. The rectifier 4| passes current upon theapplication of an input pulse to transformer 3|, as a result of whichthe condenser 35 will become charged and apply a negative bias to thegrid of the triode 40, thus biasing the triode 4|) to anode currentcut-off. When triode becomes nonconductive due to the negative charge oncondenser 35, the condenser 43 will become charged. After the charge oncondenser 35 leaks off through its shunt connected resistor 36, thetriode 40 will again pass current, at which time the condenser 43 willdischarge through the triode 40 and pass a pulse through the transformer42. In order to sharpen the output pulse, a feed-back path is providedbetween the transformer 42 and the grid circuit by means of the windingL. Thus, when condenser 43 starts to discharge, the pulse throughtransformer 42 will apply a positive impulse to the grid of the triode40, to cause the triode to pass current and dis- 6 charge the condenseri3-quicker than would otherwise be possible.

Fig. 6 shows another embodiment of a pulse delay circuit which employs atriode electrode structure 40 and a diode electrode structure 4|. InFig. 6, the triode 40' is so biased as to be normally non-conductive(that is, it passes no current in the absence of an applied pulse totransformer 3|). The application of a pulse to the transformer 3| willcause a rectified current in the output of the diode 4| which willcharge the condenser 35 in such manner as to apply a positive charge onthe grid of triode 40 through one winding of the transformer 42'. Thispositive charge on the grid of the triode 40' will cause the triode topass current until such time as the charge on condenser 35 leaks offthrough its shunt connected resistor 36 down to some lower value, atwhich time the current through the triode begins to reduce. Due toregeneration from the transformer 42' (by virtue of the feedback pathshown) the triode 40' cuts itself off suddenly and passes a pulsethrough to the output circuit. It will thus be seen that the system ofFig. 6 works in reverse compared to the systern of Fig. 5. Certainrefinements shown in Fig. 6 which are not shown in Fig. 5 include thecondenser 45 and resistor 46 combination in the anode circuit of thetriode. The condenser 45 and the main inductance coil in the anodecircuit of the triode 40 may, if desired, be adjustable for coarse timedelay adjustment, whereas the adjustment of resistor 36 provides exacttime delay adjustment. The resistor 46 can 'be replaced by a largereaetance in order to save the loss of power in the circuit.

Fig. 7 shows a pulse modulation circuit which can be employed in thesystem of Fig. l for modulating the time of the pulses. This circuit ofFig. 7 includes a pulse delayer and pulse timing modulator. Referring toFig. 7 in more detail, there is shown a triode vacuum tube 56 acrossWhose grid and -cathode are connected a circuit 5| which extends to thepulse oscillator 4 of Fig. l, and also a modulation input circuit 52which extends to the source of modulating potentials for impressingmodulations on the pulses in accordance with the intelligence to beconveyed. The modulation input circuit 52 is connected to the grid andcathode of the triode 50 through an audio frequency transformer 53. Ineffect, the vacuum tube 56 is a pulse amplifier as well as a pulsemodulator and a pulse limiter. The anode circuit of triode 50 includesan inductance 54 which stores energy therein, which energy is controlledby the tube anode current for delivery to the pulse delayer and pulsetiming modulator vacuum tube 3D. The control grid of vacuum tube 30 isconnected to the anode of the vacuum tube 5|! through a Icondenser 56. Acondenser 34 is connected between the cathode and anode of the pulsedelayer 30', while a condenser 34 is connected between the screen gridand cathode of tube 30' in substantially the same manner as the samenumbered elements of Fig. 4. It should be noted that the condensers 34and 34' have individual resistors 32 and 32 connected between them andthe positive anode polarizing potential. An adjustable resistor 5l isconnected between the cathode and control grid of tube S0' for providingan adjustment of average pulse delay.

In the operation of Fig. 7, the triode 50 is normally conductive andstores energy in inductance 54. When a negative pulse fromtheoscillator; I4 isn applied' to.l 'the' 'circuitil 5|1`and thence to thegrid of the-triode, thetube"50 willhaveits currentcut off` andlcause theapplication ofa. positive pulse to "the control' grid of the tetrode'3U. `The tetrodev 30 ris normally conductive 'inthe absence "of pulses.The application of a positive pulse'to I'thecontror'grid of thetetrode-30 will cause grid rectification whichiwill charge vcondenser 5Snegatively ori the sideL adjacentthe control grid :of the 'tet'rode 30.'Ilhe "tube `30 is lthus left in an' anode ycurrent cut-off condition.'During this condition;A the co'ndensers,A 3'4 andv 344 charge up,andbothcf these condensers will 'discharge through theitulbe 30'iwhenthe negative vcha-rgelon condenser' leals on. The operation-of vacuumtube3'0, it`willf'thus be seen, issubstfantially similar tothe'cperation' of Fig. 4 previouslydescribed. For modulationpurposes,the input to-thetriodev 59 through circuit 521 andtransformer'lB will'vary the average' bias'of the'triode `amplifierandin this rnanner vary the energy'stored in induetance L- andthestrength of 'the pulse delivered" to the te'trode,V as a resultoflwhichthe peakmharge cnr-condenser 56' Will bel varied Vin"'a'ccordai'ice withthev modulatiomthus varying the time 'delay of the output' pulse'relativel tol the input pulse. `It should'be-noted'that theenergy'stored in coil A'54' isvdeliveredl to l the delayertube 3B ateach-pulse. The anode current inthe tube 56 should, `of course, reach asubstantially steady state'value'before'each-pulse. if desired; theremaybe provided a feed-back regenerative circuit in' the 'tetrode circuitor in a later stage to sharpen the'output pulse. y

The system of Fig. 8 shows a pulse"inodula tion circuit which maybe usedin the system-'0f Fig. 1-for modulating the length of the'pulses.Thiscircuit of Fig. 8, like that of Fig. 7,'includes both thel pulsemodulator andthe pulse delayer. In addition, the system of Fig. 8'includes a pulse peak'limiter tube 152 which follows thepulse'delayer-"andlength modulator 3D" in order toIconvert'variable'amplitude pulses'fro'rn thev output of the' delayertube to variable length pulses. The pulse delayer and length modulatorherein represented by 'vacuum -tube v tetrode 33', with its associatedelements,'is substantially the lsame as that shownl in Fig- 7. It shouldbe noted that inFig. 8 the'pulse input circuit `5i is-applied betweenthe grid and cathode 4of pulse amplier tetrode vvacuum tube 60.Thefscre'en grid and cathode'bf tube 60 are `connected together througha by-pass condenserill, in turn shunt- 'ing a portionof aipotentiometercircuiti-'65. The modulation' input circuit"52, however, is .appliedin'Fig; 8 to a transformertl, -which isconnected in suchmanner that theanodesupply voltage of tetro'de v30 is modulated'in one sense-while thecontrol grid-cathode potential oftube '38 is modulated in an oppositesense for the purposefof'balancing the-effect ofthe modulation -upon thetimedelay. I'am thus able toobtain pulses' of variable vamplitude fromthe -'delayer tube-30", which-after being limitedliripulse peak limiter:tube-T62 yapp-ear as pulses of variable lengthin the output circuit 63.rIhelpulse amplifier -andlimite'r vtube Ylill is lnormally conductive inthe'absence of a negative input pulse from the oscillator-I4 applied tocircuit 5|. The application of a negative pulse to fthe circuit'5iserves to cut off the anode current 'in'tube 1till momentarily, as aresult-of which a positive '-pulse is deliveredinto the delayer tube 30"to produce grid rectification. The elements appearing in 8 Fig. 8-which'correspond in -f-uncti'on- 'to Tthose' in Fig. 'T have been givenfthe same reference numerals.

Fig. 9 shows Ainblock 'form a'multiplex receiving system for use'inreceiving the'multiplicity of short duration pulses of received energyseht out by the multiplex transmitter of Fig. 1.l The receiver includesan antenna''which is vindicative of any suitable energy 'collecting'device whichv may be directive, a heterodyne detector ll which may, ifdesired, be preceded by a radio frequencyamplier, which is` fed-withenergy from the antenna y'Ill and also with oscillations from alocal'heterodyne oscillator "I2, andan intermediate frequency amplier 13in' theoutput of the hetero'dyne detector 1i. The'intermediate frequencyamplifier 13 has its output connected over leads 14 to a pulse keyer15,r and also over leads 16 to a multiplicity of 'other' pulse keyersl1, 18; 19, etc. The pulse keyers 'l1,18',19, etc. are associated withdifferentr communication lpaths cr channels forreceiving the differenttrains or groups of pulses; each of Whichhas its own modulation. Thepulse Vkeyer 15', on the-other hand, forins'part of a pulsesynchronizing systemsynchronized mainly by the end of the receivedpulse. 'This synchronization system includes not only the pulse keyer'l5 but also the pulse rectifier and' amplifier "Sl and the pulsesynchronized pulsing oscillator-amplier 92. The output from the pulse'keyer T5 supplies its output over lead to the pulse'rectier'andamplifier 9i, the latter in turn feeding thel rectified'energy to apulse'synchronized" pulsing oscillator and amplifier 92 froinwhichenergy is returned overA leadsV 93 to the'pulsev keyer" 15. Thissynchronization system which isk described in more detail later in'connectionwith-Fig 10, operates in synchronism` with the'llrst `trainof received pulses in response to theA received pulses.

The diierent channels or" communication paths 'in which are found-the4pulse keyer 11, 'I8 and 1Q etc. 'are fed by pulse'keying controlcurrents over individual pulse delayer"circuits"8l, 88, B9, etc., the-latter Ain turn beingfed 'over leads 35 from theV output 'ofthe pulsesynchronized pulsingoscillator and arnplier 92. The pulse' delayers 87,'88 and' 89 etc. have different delays which'are adjusted to correspondto the average time spacing of the different 'series of incoming pulses.The voutputs from the pulse keyers 1l, 18, v'F9 etc; are respectivelypassed on to pulse 'integrator'anddemodulator circuits 91, QB, 99 etc.forv reproducing the signal modulation. These pulse integrators and'demodulator circuits-are preferably biasedto provide a certainthreshold'value'below vwhich no signal will be passed on to thesubsequent utilization circuit, as-an aid in eliminating' 'noise Vandinterference'belcw the' threshold value. The type'of pulse integratorcircuit will, of course, depend upon the type of modulation on thekincoming pulses. The outputs from the 'pulse integrator and demodulatorcircuits 91; .H8-and 99, etc. vare passed -onrespectivcly toA audiovamplifier and volume control Circuits 'l, lH78 and 109, from whichItheaudio output is utilized in any suitable audio translatingdevicesuchas a headphone. loudspeaker; 'recorder 'or printer.

' Briefly stated, the operation' ofthe pulse type multiplex receiver ofFig. 9fis as follows: The extremely short pulses sent out by thetransmitterlof Fig'. land-fwhichv-occupy a fsmall percentageiof the.'total' time, VareI received. on antenna 'lli and reduced infreql'ien'cy'v in-fheterodyne detector 1|, and amplified by intermediatefrequency amplifier 13. The intermediate frequency signals fromamplifier 13 pass through the pulse keyer amplier tube 15 Whose outputis rectified by 9| and the rectified pulse passed `on to thesynchronized pulsing oscillator 92, which, in turn, interrupts the pulsekeyer 15 at the frequency of the first series of received pulses. Thisrst `series of received pulses, in accordance with the preferredembodiment of the invention, is passed by the pulse delayer and keyercircuit 20 of the transmitter of Fig. 1 and thus has no modulation.

The output pulses from the pulse synchronized pulsing oscillator 92passes through the pulse delayer circuits 81, 88 and 89 whose delays areadjusted to correspond to the time spacing of the different series ofincoming pulses, each series of which represents a different channel andhas its own modulation. The signals themselves, however, pass from theoutput of the intermediate frequency amplifier 13 to the pulse keyers11, 18, 19 etc., Whose operativeness or responsiveness is controlled bythe pulse delayers 81, 88, 89 etc. It will thus be seen that thedifferent channels in the receiver are rendered operative solely atthose times When the signals are due to arrive at the differentchannels. Putting it in other Words and using the language I havepreviously adopted, the different receiver channels are shuttered orgated in synchronism with the incoming pulses and the length of gateopen periods for each channel are made only large enough to include thedesired pulses when they are modulated. The signals passed on by thepulse keyers in the different communication paths or channels are thendemodulated in the apparatus 91, 98, 9S etc., the audio output of whichis then amplied in audio amplifiers |01, |08, 109.

The synchronization system in the multiplex receiver of Fig. 9, whichoperates in synchronism with and under control of the received pulses,is illustrated in more `detail in Fig. 10, whose elements bear the samenumbered reference numerals as the corresponding elements in Fig. 9.Referring to Fig. l0, it Will be noted that pulses of radio frequencyenergy from the intermediate frequency amplifier 13 are applied betweenthe grid and cathode of the p-ulse keyer 15 through a transformer |10.The pulse keyer 15 is normally biased to cut-off by virtue of a negativepotential applied to the grid over a path including a resistor 12| and asecondary winding of transformer |10. The output from the pulse keyer isapplied to apparatus 9| Which includes a rectifier and a direct currentamplifier, as shown.

It should be noted that the grid and anode circuits of the pulse keyer15 comprise parallel tuned circuits. These tuned circuits are tuned tothe intermediate frequency signal. The pulse synchronized pulsingoscillator and amplier 02 is shown as a triode of the feed-back orregenerative type. The grid includes an inductance coil which is coupledto the feed-back coil 112 in the anode circuit of the tube, both ofthese coils, in turn, being coupled to another coil ||3 which passespositive pulses at the frequency of the pulse oscillator to the grid ofthe pulse lieyer 15 over lead llt and resistance |15. The oscillator f,in effect, is a saw-tooth oscillator Which normally operates by itselfat a frequency slightly lower than the Apulse rate of the incomingpulses, but is constrained to operate at the pulse frequency by theincoming synchronizing pulse signals. The values of the resistors andcondensers either in the grid or :plate circuits, or both, of the pulseoscillator 92 determine the frequency of the oscillations of the pulseoscillator 92 and these values together with the constants of thetransformer in the oscillator circuit determine the length of pulsesacross resistance 11| which are preferably equal to, or somewhat longerthan the transmitted pulses. The voltage across the anode condenser HSand across the grid condenser ||1 is a saw-tooth Wave although thevoltage pulse passed by coil |13 is a short lpulse Wave. Oscillator 92operates continuously Wh-ether or not incoming signals arrive at thereceiver. It is made relatively highly stable in operation. This type ofypulsing oscillator, it Will be recognized, is well known in thetelevision art. It will be found described in my Patent #1,898,181 andin Tolson and Duncan Patent #2,101,520. In the operation of thesynchronization system, the incoming pulses applied to transformer |10,which are at an intermediate frequency, will be passed by pulse keyer 15to pass them on to the rectifier and amplifier apparatus 9i only withintime intervals covered by the Ipulses from oscillator 92. As the timeperiods of signal pulses and pulses from oscillator 92 drift togetheruntil they overlap, signal pulse energy passes through keyer 15 and`pulse energy is delivered through rectifier and amplifier 01 to advancethe pulses of oscillator 92. The more the signal pulses overlap into the:pulses from oscillator 92 the longer and stronger will be the pulsesand the average D. C. current from 9| into oscillator 92 and the moreoscillator 02 will be speeded up to tend to reduce the overlap. By thismeans, after suitable adjustments, oscillator 02 is synchronized by thesignal pulses.

In this arrangement the power of energy from 9| to advance the iphaseand increase the fr-equency of oscillator 92 may be adjusted for optimumresults. In addition, by employing different time constants in 91 it ispossible to obtain any desired rate of response of oscillator Q2 toshifts of phase between signal pulses and pulses from 92. This timeconstant adjustment provides an equivalent control of averaging of thesynchronizing effect of signal pulses, equivalent to control offrequency selectivity for reducing the effects of noise arriving Withthe signals.

The connections from the pulse oscillator 9i! for supplyingsynchronizing pulses to the pulse delayers of the multiplex receiver arealso made across Winding 1 I3, each delayer being connected through aresistance like resistance 1 I5 to minimize reactions between delayersand the synchronizing system.

Fig. 11 illustrates a single pulse receiver for receiving modulatedpulses of high frequency energy transmitted from a remote pulse typetransmitter. This receiver includes an antenna which is connected to thesystem through a transmission line |50, a detector circuit 15| which isshown as a crystal detector -although it may be any suitable type ofdetector, a pair of pulse amplifiers |52, a keyer amplifier |53, anotherpulse amplifier 1%, a detector |515, an audio amplifier |51, and a pulseoscillator |53 which operates in synchronism with the received pulsesand controls the keyer amplifier |53.

In the operation of Fig. 11, let us assume that this receiver isdesigned to receive ultra high frequency pulses having a percentageduration of apDlOXmaely 1% of the total time, repeated il at a rate of20,000 per second, and .modulatedin amplitude by speech waves at thetransmitter. This 20,000 per second pulse rate is illustrative of anysuitable frequency above the highest modulation frequency.` These ultrahigh frequency pulses. are received in the antennaand passedon to. thecrystal detector over transmission line |50. The detector l5! serves toprovide in its output pulses of energy with the ultra high frequencycarrier removed, i. e., direct current pulses, or pulses more or lessrepresentative oi the envelope of radio frequency -current pulses. Thesepulses are then amplified in pulse amplifiers, |52, |53 and |54 anddemodulated in detector |55. The pulse ampliers |52, of course,havesuiicient over-all gain to acheive the desired purpose, it beingunderstood that, if necessary, additional amplier stages may be used.Theamplier of the receiver is keyed synchronously by the keyer amplierE53 and passes energy on ,to the pulse amplifier |54 and the detector|56 only when pulses are due to arrive.. The--keyer |53 is operated bypulse oscillator |58. which supplies pulses at the end of the` receivedpulses and which is synchronized by the endings 'd ofthe receivedpulses. In effect, the pulse oscillator |58is a saw-tooth oscillatorwhich operates in ,synchronism with and iscontrolled by the received`pulses. This oscillator produces short pulses, in the transformer |59which discharge the condenser X andthereby block the pulse kcyeramplifier |53, the latter in turn being arranged to receover itsoperating potentials, as condenser X charges up again through itscharging resistance, in .suflicient time for a succeeding pulse tostart. Putting it in other words, it can be sadthat the oscillator |58shutters or gates theamplier |53. The pulse. ampli'er |54 operates onthe threshold principle. Grid rectification ,inl this` amplifier |50,due to signal pulses, biases the, grid potential to such a. value thatweak .Currents such as may be produced by noise, do. n Otproduce anyoutput from the tube.

The coupling of signal pulses to oscillator |50 for accomplishingsynchronizing isObtainedfrom thescreen grid current of keyer tube |53,which responds to the signal pulses, and which reacts upon, oscillator|50.

Fig... 12 shows another type of receiver which may be employed insteadof the receiver of Fig. 11

for receiving amplitude modulated carrier wave pulses. The receiver ofFig. 12 is an alternative to the receiver of Fig. ll and both areequipped with'v the desirable feature of shuttering or gatin 1 thereceiver synchronously with the transmitter, so that the receiver isOperative solely attimes when the signal pulses are due to varrive. InFig. l2 thel antenna is shown by way of example as a horn type ofantenna for receiving ultra high frequency pulses of extremely shortduration radiated by the remote transmitter. The received impulses arepassed from the antenna through transmission line |50 to the de tector|5| which will produce direct current pulses.Y The direct current pulseoutput from the detector |5| is passed on to three switching ampliiers.|60 arranged in cascade, the output of which is passed on to a pulseintegrator detector |61 which demodulates the pulses and produces audiofrequency current which is then amplified in audio amplifier |52. Thegating or shuttering of the receiver is effected by means of thepulsecontrol switcher tube and its associated elements. It should be notedthat the controlgrid of tube |65 is connected to the out- Lil) put ofthe. last pulse switchingv amplifier' |60, while the screen gridcircuitsof the three pulse switching. ampliers |60. are connected over accmmonlead to the anode of the tube |55. In the operation of theVreceiver of Fig. 12, tube. |55, inthe absence of received pulses,.isnon-conductive, However, arrival of asignal pulse which passesthrough the receiver will 4causetube |65 to pass current therebydischarging the condensers in its anodecircuit. This reduces the screengrid potentials of amplifiers |60 and makes them inoperative for atimevperiod which is adjustable by adjusting the value` of resistance throughwhich the condensers are charged.. This. time period is adjustedtccorrespond'to the timeperiod between the received signal pulses. Thusthe receiver is blocked during time periodsv between signal pulses. Arpulse received on the receiving system and passed by the pulse switchingampliiiers places a positive potential on the control gridoftube |65,thusrenderingit momentarily conductive. The momentary conductivity of.tube lowers .the screenpotentialon the threepulse switching amplier.tubes |60, asa. result of which the receiver is. rendered inoperativeuntila selected time later when another pulse is due tor be received.The arrangemnt cffcondensers 66 and |57 in circuit with the tube|65'prevents the quick lowering of the. screen potentials` on the pulseswitching amplifiers until almost the. end of the received pulse, thusallowing substantially the entire pulse to be used in producing youtputfrom the receiver. These condensers are,` in effect, `a time delaycircuit. Putting it in other words, the keyer or switcher tubeV |65serves to discharge the screenpotentials of the pulseswitching.amplifiers |60 at each received pulse. Thesescreen potentials, however,recover or assume their normal values before thenext pulseis due toarrive.

It should be noted that tubes |60, in the absence of signal pulses,pass. no current because of bias potential on their control electrodes.lTherefore, pulses of theswitcher |65donot pass energy on to the pulseintegrator detector in the absence of a signal pulse.

The invention .claimed is:

l. A pulse delay circuit comprising an electric tube having a grid, ananode anda cathode, an inputv circuit connected between said grid andcathode, said input circuit including in series therewith a condensershunted by a resistor, a transformer having a primary vWinding connectedbetween said anode and the positive terminal of a. source ofunidirectionalpolarizing potential, and a secondary winding coupled toan output circuit, the constants of said circuit being such that saidtube normally passes anode current in the absence of a pulse applied tosaid input circuit, and aA condenser connected between said cathode andthat terminal of said primary winding farthest away from said anode,whereby the application of a pulse to said input circuit charges saidfirst condenser to bias said tube to cut-olf, thereby permitting -acharge to build up on said second condenserl discharging across saidtube when. the charge on saidrst condenser leaks off. as a consequenceof which an output pulse is produced in said transformer;

2. A pulse delay circuit in accordance with claim l., including meansfor adjusting the eective value of said resistor for varying the timedelay of the output pulse, and also an adjustablev resistor locatedbetweenv said source of polarizing potential and said primary winding.

3. A- pulse delay circuit comprising an electric tube having a cathode,a ysignal grid, a screen grid, and an anode, an input circuit connectedbetween said signal grid and said cathode, said input circuit includingin series therewith a condenser shunted by a resistor, a transformerhaving a primary winding connected between said anode and the positiveterminal of a source of unidirectional polarizing potential, and asecondary winding coupled to an output circuit, the constants of saidcircuit being such that said tube normally passes anode current in theabsence of a pulse -applied to said input circuit, a condenser connectedbetween said cathode and screen grid, and a resistive connection betweensaid screen grid and the positive terminal of said source, whereby theapplication of a pulse tosaid input circuit charges said first condenserto bias said tube to lcut-olf, thereby permitting a charge to build upon said second condenser, said second condenser discharging across saidtube when the charge on said rst condenser leaks off, as a consequenceof which an output pulse is produced in said transformer.

4. A pulse delay circuit comprising an electric tube having a cathode, asignal grid, a screen grid, and an anode, an input circuit connectedbetween said signal grid and said cathode, said input cir-cuit includingin series therewith a condenser shunted by a resistor, a transformerhaving a primary winding connected between said anode and the positiveterminal of a source of unidirectional polarizing potential, and asecondary winding coupled to an output circuit, the constants of saidcircuit being such that said tube normally pases anode current in theabsence of a pulse applied to said input circuit, a condenser connectedbetween said cathode and screen grid, and a resistive connection betweensaid screen grid and the positive terminal of said source, anothercondenser connected betwen said cathode and 'that terminal of saidprimary winding farthest away from said anode, whereby the applicationof a pulse to said input circuit charges said rst condenser to bias saidtube to cut-off, thereby permitting charges to build up on both saidsecond and third condensers, said last condensers discharging throughsaid tube when the charge on the first condenser leaks off, as aconsequence of which an output pulse is produced in said transformer.

5. A pulse delay circuit comprising an electric tube having a grid, ananode and a cathode, an input transformer having one winding connectedto a source of pulses and another winding coupled between said grid andcathode, an output transformer having one winding connected between saidanode and the positive terminal of a source of unidirectional polarizingpotential, and a secondary winding coupled to an output circuit, theconstants of said circuit being such that said tube is normallyconductive in the absence of a pulse applied to said input transformerby said source of pulses, and a condenser connected between said cathodeand that terminal of said primary winding farthest away from said anode,whereby the application of a pulse to said input transformer biases saidtube to cutoff, thereby permitting a charge to build up on saidcondenser, said condenser discharging across the primary winding of saidoutput transformer when the cut-off bias on said tube leaks off.

6. A pulse delay circuit comprising an electric tube having a grid, ananode and a cathode, an input circuit connected between said grid andcathode, said input circuit having in circuit therewith a condensershunted by a resistor, a transformer having one winding connectedbetween said anode and the positive terminal of a source ofunidirectional polarizing potential, and another winding coupled to anoutput circuit, the constants of said circuit being such that said tubenormally passes anode current in the absence of a pulse applied to saidinput circuit, and a condenser connected between said cathode and thatterminal of said one winding farthest away from said anode, whereby theapplication of a pulse to said input circuit charges said iirstcondenser to bias said tube to cut-off, thereby permitting a charge tobuild up on said second condenser, said second condenser dischargingacross said tube when the charge on said first condenser leaks olf, as aconsequence of which an output pulse is produced in said transformer.

7. A pulse delay circuit comprising an electric tube having a grid, ananode and a cathode, an input circuit connected between said grid andcathode, said input circuit having'in circuit therewith a rectifieracross which is a condenser shunted by a resistor, a transformer havingone winding connected between said anode and the positive terminal of asource of unidirectional polarizing potential, and another windingcoupled to an output circuit, the constants of said circuit being suchthat said tube normally passes anode current in the absence of a pulseapplied to said input circuit, and a condenser connected between saidcathode and that terminal of said one winding farthest away from saidanode, said input circuit also including a coil coupled to said windingsof said transformer to provide a feedback path to the grid, whereby theapplication of a pulse to said input circuit charges said rst condenserto bias said tube to out-off, thereby permitting a charge to build up onsaid second condenser, said second condenser discharging across saidtube when the charge on said first condenser leaks off, as a consequenceof which an output pulse is produced in said transformer.

8. A pulse delay circuit comprising a vacuum tube having anode, grid andcathode electrodes, a transformer having a rst winding coupled betweensaid anode and the positive terminal of a source of unidirectionalpotential, a second winding coupled to an output circuit, and a thirdwinding having one terminal coupled to said grid and another terminalcoupled to said cathode through a variable resistor shunted by acondenser, a rectifier coupled across said variable resistor-shuntcondenser combination, and means for supplying recurrent input pulses tosaid rectif-ler.

9. A pulse delay circuit comprising a vacuum tube having anode, cathode,control grid and screen grid electrodes, a condenser between the screengrid and cathode, a direct connection from said cathode to a point ofreference potential, a plurality of serially arranged impedance elementscapable of passing direct current connected between said anode andscreen grid, a condenser connected between said screen grid and saidcathode, a circuit including a variable resistor for applying inputpulses between said control grid and cathod, and an output circuitcoupled to said anode for deriving time delayed pulses.

l0. A pulse delay circuit in accordance with claim 9, including atransformer in the input circuit.

11. A pulse delay circuit in accordance with claim 9, characterized inthat at least one of said seriallyr arranged impedance'elements is avariable resistor.

12.n A pulseidelay circuit arrangement including a controlled electronflowstructure having at least a Vcommon electrode andan electroncollectingv electrode defining .an electron ilow path and a controlelectrode arranged in said structure `to control the flow of electronsin said electron :flow path, an output load impedance elementconnectedtosaid electron collecting electrode, an velectron storagecapacitor coupled in series with said-.output load impedance element andsaid electron flow path and connected to said impedance element at aopint remote from said collecting electrode, a pulsevinput circuitcomprising a shunt capacitor-resistor combination coupled between saidcontrol and said common electrodes,said circuit arrangement havingvconstantsat which the electron flow in said structure is normally ofone of two predetermined conditions opposite in nature, wherebyapplication-of a pulse-to said input circuit charges said shuntcapacitor to alter the electron lowin said structure to charge saidelectron storage capacitor, the charge on said storage capacitor beingdischarged across said electron flow path upon the charge on said shuntcapacitor being discharged through said shunt resistor, therebyproducing an output pulse at said load impedance element.

13. A pulse delay circuit arrangement including ari-.electron dischargestructure having at least a cathode and an anode electrode defining anelectron discharge path and a control electrode arranged in saidstructure to control the flow of electrons in said electron dischargepath, an output load impedance element connected to said anodeelectrode', an electron storage capacitor coupled in series with saidoutput load impedance element and said electron discharge path andconnected `to said impedance element at a point remote from said anodeelectrode, a pulse input circuit comprising a shunt capacitor-resistorcombination coupled between said control and said cathode electrodes,said circuit arrangement 'having constants at which the electron ilow insaid structure is normally `of one of two predetermined conditionsopposite in nature, whereby application of a pulse to said input circuitcharges said shunt capacitor to alter the electron flow in saidstructure to charge said electron storage capacitor, the charge on saidstorage capacitor being discharged across said electron discharge pathupon the charge on said shunt capacitor being discharged through saidshunt resistor, thereby producing an output pulse at said load impedanceelement.

14. A pulse delay circuit arrangement including a controlled electronflow structure having at least a common electrode and an electron co1-lecting electrode defining an electron flow path and a control electrodeyarranged in said structure to control the flow of electrons in saidelectron path, an output load impedance element connected to saidelectron collecting electrode, an electron storage capacitor coupled inseries with said output load impedance element and said electron iiowpath and connected to said impedance element at a point remote from saidcollecting electrode, a pulse input circuit comprising a shuntcapacitor-resistor combination coupled between said control and saidcommon electrodes, said circuit arrangement having constants at whichelectrons flow in said structure, whereby application of a pulse to saidinput circuit charges said `shunt .capacitor to .block theelectron, flowinv said structure to charge said electron storage capacitor, the chargeon said .storagecapacitor being discharged across said electron Ilowpath upon the charge on .said shunt capacitor being discharged .throughsaid shunt resistor, thereby producing an output pulse at said loadimpedance element.

15. A pulse delay circuit arrangement including an electron dischargedevice having at least cathode, control and anode electrodes dening anelectron discharge path having a control electrode arranged therein tocontrol the flow of electrons in said electron discharge path, an outputload impedance element connected to said anode electrode, an electronstorage capacitor coupled vin series with said output load impedanceelement and said. electron .discharge path and connected to saidimpedance element at a point remote from said anode electrode, a pulseinput circuit comprising ashunt capacitor-resistor combination coupledbetween said control and said cathode electrodes, said circuitarrangement yhaving constants at which electrons normally flow in saiddevice in the absence of pulses in said input circuit, wherebyapplication of a pulse to said input circuit charges said shuntcapacitor to block the electron now in said device to charge saidelectron storage capacitor, the charge on said storage capacitor beingdischarged across said electron discharge path upon the charge on saidshunt capacitor being discharged through vsaid shunt resistor, therebyproducing an output pulse at said load impedance element.

16. A pulse delay circuit arrangement including an electron dischargesystem having at leasta cathode and an anode deiining an electrondischarge path and a control grid and a screeny grid interposedtherebetween to control the flow of electrons in said electron dischargepath, an. output load impedance element connectedy to said anode, aresistance element and an. electron storage capacitor coupled in serieswith said output load impedance element and said electron Vdischargepath and connected to said impedance element at a point remote from saidanode, said screening grid being connected to the junction between saidcapacitor andsaid resistance element, a pulse input circuit comprising.a shunt capacitor-resistor combination coupled between said controlgrid and said cathode, said circuit arrangement having constants atwhich said electron discharge system normally passes current in theabsence of pulses in said input circuit, whereby application of a pulseto said input circuit charges said shunt capacitor to alter the electrondischarge in said system to charge said electron storage capacitor, thecharge on said storage capacitor being discharged across said electrondischarge path upon the charge on said shunt capacitor being dischargedthrough said shunt resistor, thereby producing an output pulse at saidload impedance element.

17. A pulse delay circuit arrangement including an electron dischargesystem havingv at least a cathode and an anode defining an electrondischarge path and a control grid and a screen grid interposedtherebetween to control the now of electrons in said electron dischargepath, an output load impedance element connected to said anode, a sourceof unidirectional operating potential, said cathode being connected tothe negative terminal of said source of operating potential, an electronstorage capacitor coupled in series with said output load impedanceelement and said electron discharge path and connected to said impedanceelement at a point remote from said anode, an auxiliary storagecapacitor and a resistance element coupled in series between saidcathode and the positive terminal of said source of operating potential,said screening grid being connected to the junction between saidauxiliary capacitor and said resistance element, a pulse input circuitcomprising a shunt capacitor-resistor combination coupled between saidcontrol grid and said cathode, said circuit arrangement having constantsat which said electron discharge system normally passes current in theabsence of pulses in said input circuit, whereby application of a pulseto said input circuit ycharges said shunt capacitor to alter theelectron discharge in said system to charge said electron storagecapacitor, the charge on said storage capacitor being discharged acrosssaid electron discharge path upon the charge on said shunt capacitorbeing discharged through said shunt resistor, thereby producing anoutput pulse at lsaid load impedance element.

18. A pulse delay circuit arrangement including a controllable electronflow structure having at least an electron emitting electrode and anelectron collecting electrode defining an electron ilow path and anelectron flow control electrode interposed therebetween to control theflow of electrons in said electron flow path, a shunt network comprisinga capacitor and a resistor connected in parallel, a direct current pathfrom one end of said network to the electron emitting electrode of saidelectron flow structure, direct current connections between the otherterminal of said network and the control electrode of said electron flowstructure, a pulse input circuit coupled to said network to charge saidcapacitor, a pulse output impedance element connected to the electroncollecting electrode of said electron flow structure, said circuitarrangement having constants at which the electron flow in saidstructure is normally of one of two predetermined conditions opposite innature and upon application of a pulse to said network the charge onsaid capacitor is effective to reverse the condition of electron flow insaid structure, at least one reactive circuit component coupled betweenthe electron emitting and electron flow control electrode circuit andthe electron collecting electrode circuit to cause a pulse of current toflow in said pulse output impedance element upon the discharge of saidcapacitor and the reinstatement of said one condition of electron now insaid structure, thereby producing an output pulse at the outputimpedance element delayed in time with respect to the application of apulse to said input circuit.

19. A pulse delay circuit arrangement including a controllable electronow structure having at least an electron emitting electrode and anelectron collecting electrode defining an electron flow path and anelectron flow control electrode interposed therebetween to control theflow of electrons in said electron flow path, a shunt network comprisinga capacitor and a variable resistor connected in parallel, a directcurrent path from one end of said network to the electron emittingelectrode of said electron flow structure, direct current connectionsbetween the other terminal of said network and the control electrode ofsaid electron flow structure, a pulse input transformer having asecondary winding thereof coupled to said network to pass a pulse ofcurrent through said network to charge said capacitor, a pulse outputtransformer having a primary winding with one terminal thereof connectedto the electron collecting electrode of said electron flow structure andthe other terminal connected to a source of polarizing potential, saidcircuit arrangement having constants at which the elec'- tron ilow insaid structure is normally of one of two predetermined conditionsopposite in nature and upon application of a pulse to said network thecharge on said capacitor is effective to reverse the condition ofelectron low in said structure, at least one reactive circuit componentcoupled between the electron emitting and electron flow controlelectrode circuit and the electron collecting electrode circuit to causea pulse of current to fiow in said pulse output transformer winding uponthe discharge of said capacitor and the reinstatement of said onecondition of electron flow in said structure, thereby producing anoutput pulse at the output transformer delayed in time with respect tothe application of a pulse to said input transformer.

20. A pulse delay circuit arrangement includnig a controllable electronflow structure having at least an electron emitting electrode and anelectron collecting electrode dening an electron now path and anelectron flow control electrode interposed therebetween to control theow of electrons in said electron flow path, a shunt network comprising acapacitor and a resistor connected in parallel, a direct current pathfrom one end of said network to the electron emitting electrode of saidelectron flow structure, direct current connections between the otherterminal of said network and the control electrode of said electron flowstructure, a pulse input circuit, a diode element coupling said pulseinput circuit across said network to charge said capacitor uponapplication of a pulse to said input circuit, a pulse output transformerhaving a primary Winding connected to the electron collecting electrodeof said electron flow structure and a secondary winding connectedbetween said electron flow control electrode and the other end of saidnetwork, said circuit arrangement having constants at which the electronflow in said structure is normally blocked and upon application of apulse to said network the charge on said capacitor is effective toeffect electron flow in said structure to cause a pulse of current toflow in said pulse output transformer primary winding upon the dischargeof said capacitor and the blocking of electron flow in said structure,thereby producing an output pulse at the output transformer delayed intime with respect to the application of a pulse to said input circuit.

21. A pulse delay circuit arrangement including a controllable electronflow structure having at least an electron emitting electrode and anelectron collecting electrode defining an electron fiow path and anelectron flow control electrode interposed therebetween to control thenow of electrons in said electron iiow path, a shunt network comprisinga capacitor and a variable resistor connected in parallel, a resistivepath from one end of said network to the electron emitting electrode ofsaid electron flow structure, a rectifier, a pulse input transformerhaving a secondary winding thereof coupled in series with said rectifieracross said network to charge said capacitor on application of a pulseto said input transformer, a pulse output transformer having a primarywinding with one terminal thereof connected to the electron collectingelectrode of said electron fiow structure and a secondary windingconnected in regenerative polarity, a parallel resistorcapacito`rcombination connected between the other terminal of said primary windingand a source oipolarizing potential, said circuit arrangement havingconstants at which the electron flow in said structure is normallyblocked and upon application of a pulse to said network the charge onsaid capacitor is effective to eiect electron flow in said struc'ture tocause a pulse of current to iiow in said pulse outputtransformer primarywinding upon the discharge oi said capacitor and the reblocking ofelectron flow in said structurey thereby producing an output pulse atthe output transformer' primary winding delayed in time with respect totherapplication of a pulse to said input transformer.

22. A pulse delay circuit arrangement including a controllable electronow structure having at least an electron emitting electrode and anelectron collecting electrode defining an electron flow path and anelectron now control electrode and a screen electrode interposedtherebetween to control the iowof electrons in said electron flow path,a shunt network comprising a. capacitor and a variable resistorconnected in parallel and having one end connected to the elect-ronemitting electrode ci said electron flow structure, a pulse inputtransformer having a secondary winding thereof coupled between the otherterminal of said network and the control electrode of said electron iiowstructure to charge said capacitor upon application of a pulse to saidinput transn former, a pulse output transformer having a winding withone terminal thereof connected to the electron collecting electrode ofsaid electron ow structure andthe other terminal connected to a sourceof polarizing potential, said circuit arn rangement having constants atwhich the electron iiow in said structure is normally conducting andupon application of a pulse to said network the charge on said capacitoris effective to block the electron flow in said structure, a storagecapacitor coupling the electron emitting and screen electrodes, anadjustable resistor coupling the screen electrode to the electroncollecting electrode circuit at a point beyond the Winding of saidoutput transformer said storage capacitor being charged when saidelectron flow isv blocked and discharged across said electroniiowstructure upon the .discharge of said capacitor across said variableresistor to reinstate said electron flow in said structure to .cause apulse o1" current to flow through said pulse output transformer winding,thereby producing an output pulseat theoutput transformer delayed intime withrespect to the application of. a pulse to said-inputtransformer.

23. A pulse delay circuit including a controlled electron i'low systemhaving at least two electrodes deiining an electron fiow path the firstone of said electrodes being an output electrode, and the second beingconnected to a point of fixed potential. and a third electrodeassociated with said two electrodes to control the flow of electrons insaid path, an output load impedance element connected to said outputelectrode, a storage capacitor coupled in series circuit relationshipwith said load impedance element and said electron flow path, a pulseinput circuit having a series capacitor therein coupled between saidthird electrode and said point of fixed reference potential, saidcircuit having constants at which the electron flow in said system is ofone nature, whereby the application of a pulse to said input circuitrenders the electron flow of opposite nature to charge said storagecapacitor and said series capacitor, said storage capacitor dischargingover said electron path when the charge on said series capacitor leaksoli thereby producing an output pulse at said load impedance element.

24. A pulse delay circuit comprising a vacuum tube having an anode, acathode, a signal grid and a further grid, a capacitor connected betweenthe further grid and the cathode, a direct connection from said cathodeto a point of reference potential, a pair ci serially arrangedimpedances capable of passing direct current connected between saidanode and a source of unidirectional potential, a capacitor connectedbetween the junction point of said pair of impedances and said cathode,a circuit including a series capacitor and a resistor in shunt theretofor applying input pulses between said control grid and cathode, and anoutput circuit coupled to said anode for deriving time delayed pulses.

CLARENCE VJ. HANSELL.

References Cited in the file of this patent UNITED STATES PATENTSNumber' Name Date 1,573,983 Mathes Feb. 23, 1926 2,313,906 Wendt Mar.16, 1943 2,403,561 Smith July 9, 1946 2,418,375 Tourshou Apr. 1, 19472,451,997 Undy Oct 19, 1948 2,478,920 Hansell Aug. 16, 1949

